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Goal

The prover covinces the verifier that they know a correct witness such that for public input .

High-Level Structure

  1. Preprocessing phase: Both and obtains preprocessed polynomials and representing the circuit constraints . This step can be done offline before the input is known.
  2. Encoding the input: Once the statement is known, both and construct a low-degree polynomial encoding .
  3. Committing to the witness: sends a witness-carrying polynomial encoding , , and all the intermediate wire values while evaluating .
    • This commitment works in a gate-by-gate fashion, i.e. is the left input, is the right input, is the output of the gate . This commitment is oblivious to the wiring.
  4. and perform the following subprotocols:
    • Input Check: (realized by Zero Check on )
      • Ensures that the input wires of are consistent with the input .
    • Gate-by-Gate Check: (realized by Zero Check on )
      • Ensures that each gate is correctly computed (left input wire gate right input wire = output wire).
    • Wiring Check: (realized by Prescribed Permutation Check on , with prescribed permutation that encodes the circuit wiring)
      • Ensures that , which is quite redundant (contains each wire value multiple times, once for every time it plays an input/output role in some gate), is correct, i.e. the same wire contains the same value at each of its occurrences.
      • for example, if the wiring requires , say, is an output wire and and are input wires to some other gate, which are wired to , then is a permutation that includes the cycle , i.e. .

Where is the magic?

  • The polynomial carries the entire “computational trace” for via Lagrange interpolation. It is structured elegantly in such as way the subsequent subprotocols can obtain any intermediate wire value by evaluating at a right position.
  • Input Check and Gate-by-Gate checks are rather straightforward.
  • Wiring Check is the most involved part. One way to approach it: Understand relation between the circuit topology and permutation: Essentially, the subprotocol can make sure that the traces committed to in the polynomial are correctly positioned according to the circuit topology. It is easy to check that the circuit topology can be naturally described by some permutation e.g. the output of gate matches the left input of gate , the output of gate matches the right output of gate , etc.